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Microprocessor Design |
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Michael Buckley
Microelectronics Search and Consulting.
Recognized as one of the most successful of the nations top executive
recruiters in the Microelectronics industry, Mike Buckley has established
a reputation for success with executives and Human Resource organizations
from the Silicon Valley to the High Tech Marketplace of New England.
As the Silicon Valley has become synonymous with the Microelectronics industry,
Mike has become a reliable source for technical talent that has shaped
many semiconductor companies nationwide.
Combining his technical expertise with his in-depth knowledge of the
industry's trends and movements, Mike is a vital source for the leaders
in the chip business. In addition to establishing exclusive relationships
with industry giants, Mike has contributed significantly to the industry's
growth through his work with successful start-ups.
Mike has enjoyed a distinguished career with a total of over 15 years
experience in our industry. He has developed a specialization which
caters to the Microelectronics/Integrated Circuit industry nationwide.
Listed below are the major areas of specialization Mike Buckley supports
on a national level.
Multimedia Design and Development
Graphics Design and Development
Microcontroller Design and Development
Analog/Mixed-Signal IC Design
DSP Design and Development
Wireless IC Design
Full Custom (transistor level) IC Design
Computer Architecture / Microarchitecture
ASIC/Logic Design
CAE Design Automation
IC Layout Design
Engineering Management, Marketing / Executive Search
Logic design and VLSI Implementation on Next Generation Microprocessor.
Austin and Silicon Valley, CA
Specific Job Functions: Perform gate level logic design for a next
high- speed processor. Responsibilities include working with the RTL developer
to ensure the micro-architecture is consistent with an aggressive high clock
frequency, implementation and working with circuit team to define and integrate
transistor level blocks. Own floor planning, logic design, timing, logic
verification, electrical verification, and physical integration of the design.
Preferred Education And Experience: BS and 7+ years experience, MS and
5+ years experience, or Ph.D and 1+ years experience desired. Must have
strong logic and/or digital custom circuit design background; experience
with CAD tools for high-performance design desirable.
I/O Designers (All Levels open now, need 3-5)
Austin, TX
Responsibilities: Deliver full custom I/O blocks and coordinate
the associated integration into a microprocessor design environment. Interact
with package and board design resource regarding CPU and bus specification
and signal integrity. Define functional specifications and models for full
chip simulations and logical verification. Drive I/O development ranging
from feasibility to design margining to productization. This role will also
include circuit specification, schematic entry, layout, timing analysis,
power estimation, checks, block reviews, and documentation. Additional responsibilities
will include mentoring junior engineers, driving methodology and participating
in other global circuit, integration and technology issues.
Specific Job Functions: Good teamwork, communication,
and team leadership skills. 3 or more design cycles in microprocessor design
(from microarchitecture through production). Experience in computer architecture,
logic design, digital circuit design, high-speed I/O design, silicon debug
and productization are required. A strong background in semiconductor fundamentals,
state of the art circuit and logic design, electromagnetics, is required.
Some experience with team leadership and management is required. Experience
with high-speed circuit design tools (Spice, schematic capture, layout,
extraction, verification, and back-end) is required. Experience with package
design, signal integrity, technology issues, and analog/mixed-signal circuit
design are highly desirable.
Preferred Education And Experience: BS + 9yr, MS + 7yr, or
PhD + 4 yr.
Senior Logic Implementation/Physical Design
Silicon Valley, CA
First position:
Description Of Position: Engineer would be involved in
design efforts responsible for high-speed logic design and physical implementation
of a subsection of my clients high-performance microprocessor. Would also
be expected to contribute to global issues such as timing, global electrical
issues, and the design methodology.
Specific Job Functions: Experience in microprocessor design,
high-speed logic design, custom place and route, and timing optimization
is required. Technical management skills are a plus. Good working knowledge
of verilog, low power design techniques, gate-level design/verification,
timing analysis and optimization, electrical reliability analysis and physical
design. Knowledge of various circuit issues such as signal coupling/noise,
IR, electromigration is desired. Experience with methodology definition and
development, and tool scripting (example Perl) is a plus. Working knowledge
of industry CAD tools related to timing analysis, circuit analysis and place
& route is desired. Solid knowledge of computer architecture and circuit
issues/analysis is a bonus, though a basic working knowledge of these areas
is essential.
Preferred Education And Experience: A minimum of a BS
in Electrical engineering or a related field, and 7+ years of relevant work
experience is required. Requires demonstrated technical expertise in high-speed
logic and physical design for microprocessors.
Second position:
Description Of Position: Logic design and VLSI implementation
on next generation microprocessor.
Specific Job Functions: Perform logic design for AMDFs
next high-speed processor. Responsibilities include floor planning, logic
design, timing, logic verification, electrical verification, and physical
integration of the design. Activities include: making performance/power/area
tradeoffs, functional partitioning, interface definition, defining data path
and control block functionality. RTL development and debugging. Working with
circuit designers to make implementation tradeoffs. Providing technical expertise
for less experienced engineers.
Preferred Education And Experience: BS and 9+ years experience,
MS and 7+ years experience, or Ph.D and 4+ years experience desired. Needed
experience in ASIC SOC RTL design, synthesis, place and route. Previous
experience in the following areas a plus: Multimedia, MPEG, HW Security,
Serial protocols, IDE STATA, DDR SDRAM or static memory controllers.
Senior Circuit Designers
Austin and Silicon Valley (preferred experience in Array/SRAM, Cache design)
Description Of Position: Designs advanced complex integrated
circuits from product definition through production transfer.
Specific Job Functions: Interfaces with Applications
Engineering and marketing to determine architecture of complex new products.
Review all methods appropriate in developing complex new products and independently
selects the best method of achieving desired performance and function goals.
Oversees and helps with performance models to evaluate architectural tradeoffs
at the chip and system levels. Also helps with RTL level models of the design
working with circuit designers to meet cycle time and power requirements.
Interfaces jointly with Circuit Designers and Process Development to develop
new technology structures and design rules for new device. Provides technical
support to Marketing and Applications to help in product promotion, special
customer and product definition for complex and advanced new product design.
Preferred Education And Experience: BS and 9+ years
experience, MS and 7+ years experience, or Ph.D and 4+ years experience
desired. Requires demonstrated technical expertise in the development of
complex state-of-the-art integrated circuits and mask designs.
Microprocessor Physical Design
Austin, TX
Description Of Position: Perform tasks related to
the top-level integration of a high-speed microprocessor design. Work closely
with the various design groups and physical design team to incorporate the
chip's sub-blocks into a full chip build. Provide assistance for top-level
debug of physical verification.
Specific Job Functions: 1. Work with design team on
top-level design floor plan and maintain/update floor plan data as design
progresses. 2. Work closely with CAD team to develop and enhance chip integration
flow. 3. Perform chip level integration of design. This includes building
top level from lower level blocks, planning top-level meshes, and working
package related issues. 4. Providing assistance to other teams with regards
to debugging and fixing physical verification issues (DRC/LVS/ERC) at block
and top level. 5. Experience with physical verification (e.g. Calibre),
APR tools, IR analysis, and custom layout design. 6. Experience in scripting
(e.g. Perl) and web reporting desired.
Preferred Education And Experience: BSEE w/5+ year’s
experience, MSEE/PhD w/3+ years experience.
Senior CAD Engineers
Austin, TX
Description Of Position: Develop and support CAD
applications in support of microprocessor development.
Specific Job Functions: Experience in development
of custom microprocessor computer aided design applications. Skilled in
circuit design and analysis, physical design, systems analysis, algorithms
and programming. C/C++, Perl experience desired.
Preferred Education And Experience: BS and 7+ years
experience, MS and 5+ years experience desired. Skilled in circuit design
and analysis, physical design, systems analysis, algorithms experience required.
Programming in C/C++ is highly preferred for this role.
CPU Architects
Austin, TX
Description Of Position: Architects integrated
circuits from product definition through production transfer.
Specific Job Functions: Works with applications
engineers and marketing in product definition and developing functional
specifications consistent with process capabilities. Develops performance
models to evaluate architectural tradeoffs at the chip and system level.
Develops RTL level models of the design working with circuit designers to
meet cycle time and power requirements. Consults with circuit design engineers
who develop logic/circuit schematics and detailed lists of device geometries
suitable for use by mask designers. Works with diagnostic engineers who
develop test specifications for the products, recommends functional tests,
and approves initial test programs and patterns. Helps with debug of RTL
and gate level models and lab and tester debug. Works with Marketing and
Applications on special customer requirements. Analyzes design and performance
trade-offs and makes recommendations to improve product yield performance
or reliability. Oversees redesign of existing products performed by less
experienced engineers. Acts as project leader assuming coordinating responsibilities.
Preferred Education And Experience: BS/BA and
5+ years experience, or MS/MA/MBA and 3+ years industry experience, or Ph.D
desired. Requires demonstrated circuit design ability and thorough working
knowledge of mask design and circuit design rules.
CAD Fellow Position (VERY Senior)
Silicon Valley, CA
Description Of Position: Designs, implements,
and maintains CAD software used for physical implementation of high performance
microprocessor designs especially in the area of advisory tools (analysis
and optimization) to improve performance & reliability, reduce power
and area, through better logic to gate mapping, sizing and improved place
and route quality, while shortening the design cycle.
Specific Job Functions: Key Functions: 1. Performs
tool/flow definition, high level system and module design, module coding
and debugging, documentation system integration, and acceptance testing.
2. Leads software evaluation and design code reviews. 3. Interfaces with
user community in project definition and product qualification phases. 4.
Coordinates with other CAD engineers to ensure design integration. 5. Maintains
and enhances existing software. 6. Prepares training materials and conducts
user training sessions. 7. Acts as project leader on specific projects. 8.
Works on related projects and/or assignments as needed.
Problem Solving:
1. Develops an effective working relationship with CAD users and developers.
2. Develops an efficient and cost effective software product.
3. Improves existing algorithms.
Decision Making:
1. Determines algorithms.
2. Develops system design architecture.
Preferred Education And Experience: A technology
related Bachelor's degree or equivalent combination of training and experience
plus 9 years relevant experience in physical design and/or CAD tool/flow
development. A Master's Degree plus 7 years experience is preferred. Degrees
in electrical engineering or computer science preferred. Requires demonstrated
technical experience and good working knowledge of engineering software development
or support and computer programming. Requires effective communications skills.
Senior Physical Design/Chip Integration
Silicon Valley, CA
First Position:
Description Of Position: Job description: Develop,
maintain and support users of techfiles, regression structures, scripts
and flows for Physical Verification of std cells/macro libraries, major
blocks and full chip microprocessor designs. This includes LVS, DRC, ERC,
Dangle and Boundary Rule Checks. Develop, maintain and support Calibre and
Perl code (or equivalent) for layer generation and data manipulation at all
levels of the design. This includes implants and LEF generation, power plane/clock
generation and manipulation of metal and via layers. Participate and own
chip integration efforts of various tapeouts. This includes working with
the implementation team to debug Physical Verification issues of P&R
blocks, block combinations and full chip. This also includes doing the physical
build of entire microprocessor designs and getting them ready for tapeout/fracturing.
Specific Job Functions: Develop and maintain Calibre
and Perl code (or equivalent). Support and train users of this code. Debug
LVS and DRC errors. Coordinate work to resolve chip integration issues between
different members of the integration team.
Preferred Education And Experience: BS and 3+
years experience desired. Requires demonstrated technical expertise in Physical
Verification of microprocessor designs. Experience with programming in Calibre,
Perl and Linux (or equivalent) is a requirement. Experience with custom
or P&R physical design is a plus. Requires good communication skills.
Second position:
Description Of Position: Engineer would be involved
in design efforts responsible for high-speed logic design and physical implementation
of a subsection of my clients high-performance microprocessor. Would also
be expected to contribute to global issues such as timing, global electrical
issues, and the design methodology.
Specific Job Functions: Experience in microprocessor
design, high-speed logic design, custom place and route, and timing optimization
is required. Technical management skills are a plus. Good working knowledge
of verilog, low power design techniques, gate-level design/verification,
timing analysis and optimization, electrical reliability analysis and physical
design. Knowledge of various circuit issues such as signal coupling/noise,
IR, electromigration is desired. Experience with methodology definition and
development, and tool scripting (example Perl) is a plus. Working knowledge
of industry CAD tools related to timing analysis, circuit analysis and place
& route is desired. Solid knowledge of computer architecture and circuit
issues/analysis is a bonus, though a basic working knowledge of these areas
is essential.
Preferred Education And Experience: A minimum
of a BS in Electrical engineering or a related field, and 7+ years of relevant
work experience is required.
Third position:
Description Of Position: Develop and maintain
Calibre and Perl code (or equivalent). Support and train users of this code.
Debug LVS and DRC errors. Coordinate work to resolve chip integration issues
between different members of the integration team.
Specific Job Functions: Develop, maintain and
support users of techfiles, regression structures, scripts and flows for
Physical Verification of stdcells/macro libraries, major blocks and full
chip microprocessor designs. This includes LVS, DRC, ERC, Dangle and Boundary
Rule Checks. Develop, maintain and support Calibre and Perl code (or equivalent)
for layer generation and data manipulation at all levels of the design.
This includes implants and LEF generation, power plane/clock generation
and manipulation of metal and via layers. Participate and own chip integration
efforts of various tapeouts. This includes working with the implementation
team to debug Physical Verification issues of P&R blocks, block combinations
and full chip. This also includes doing the physical build of entire microprocessor
designs and getting them ready for tapeout/fracturing.
Preferred Education And Experience: BS and 5+
years experience desired. Requires demonstrated technical expertise in Physical
Verification of microprocessor designs. Experience with programming in Calibre,
Perl and Linux (or equivalent) is a requirement. Experience with debugging
LVS/DRC is a requirement. Experience with custom or P&R physical design
is a plus. Requires good communication skills.
Senior Microprocessor Design Verification Engineers
Silicon Valley, CA
Description
Of Position: Develop functional verification strategy for complex state-of-the-art
microprocessor designs. Provide technical expertise and strategic direction
for developing the functional verification strategy for current and next generation
microprocessor designs. Maintain and enhance existing functional verification
methodology. Improve existing infrastructure. Work on related projects and/or
assignments as needed, to meet team goals. Act as a project leader on specific
projects and provide leadership and guidance to junior engineers in the team.
Perform project definition, training and documentation. Develop quality,
timely and cost effective solutions, very independently. Interface with architects
and CMD/TMD RTL/logic designers. Develop an effective working relationship
with parties involved.
Qualifications: Requires demonstrated technical
expertise in functional verification of microprocessor designs. Experience
with Verilog HDL, programming in Perl, C/C++ and UNIX, logic simulation
is a requirement. Direct experience with Verilog simulators is a plus. Requires
good understanding of computer architecture and assembly programming. Requires
good communication skills.
Specific Job Functions: Develop environments for
stand alone block level functional validation and help debug and correct
functional errors in the HDL/logic model, using simulation tools, debug tools
and programming skills, based on in-depth understanding of the architecture
and HDL/logical design of the microprocessor. Develop an automated regression
infrastructure setup for functional verification of high-speed microprocessor
designs. Develop/run directed tests for current and new microprocessor instructions
and develop/use random excercisors, to validate functionality of microprocessor
designs. Debug regression fails at the RTL and gate level.
Preferred Education And Experience: BS and 7+
years experience, MS and 5+ years experience, or Ph.D and 1+ years experience
desired. Requires demonstrated technical expertise in functional verification
of microprocessor designs. Experience with Verilog HDL, programming in Perl,
C/C++ and UNIX, logic simulation is a requirement. Direct experience with
Verilog simulators is a plus. Requires good understanding of computer architecture
and assembly programming. Requires good communication skills.
Senior Mask (Layout Design)
Silicon Valley, CA
Description Of Position: Produces complex
and non-routine layouts of integrated circuit components from circuit schematics,
logic diagrams, netlists or other forms of circuits descriptions. May include
padring design, datapath design, Ram, ROM, etc. Coordinates efforts of other
designers for all aspects of project.
Specific Job Functions: Provides leadership
in determining best layout methodology for the block or chip based on electrical
performance, area, yield, reliability, and schedule issues. Oversees and coordinates
activities of other designers in all aspects of project including floorplan,
layout, verification. Initiates new process/procedures. Develops and implements
advance layout tools and techniques using high level programming languages
and vendor supplied application specific languages. Interfaces with Design
Engineering to plan and develop layout strategy and layout time table. Utilizes
advanced functions of computer aided design (CAD) systems to perform circuit
component layout and verification, including place and route tools. Maximizes
the use of CAD tools in performing IC layout. This includes floorplanning
tools, datapath tools, and other layout tools. Oversees the design and implementation
of macros and programs to enhance the layout process and to ensure layout
correctness by eliminating redundant tasks and human error. Advises Design
Engineering on the layout implication of various design alternatives.
Preferred Education And Experience: A technology-related
bachelor's degree or equivalent combination of training and experience plus
5 years of directly related mask design experience. Experience must include
the layout of highly complex integrated circuits with extensive knowledge
of design/product trade- offs. Requires effective communication skills.
~~~Additional Needs~~~
I am also engaged in a search for the following
positions, please call me for more information on these position if you are
interested!
a) Senior I/O Designers with experience
in DDR Design, Silicon Valley, CA
b) Senior Cad Flow/Methodology Engineer, Perl, strong S/W Development
skills, Silicon Valley
c) Senior CAD Electrical Analysis Engineer, Silicon Valley, CA
d) Senior CAD, Engineer, Placement, layout, Placement algorithms, Silicon
Valley, CA
e) 3-4 Senior RTL/Logic Designers, Austin, TX
f) CAD/EDA engineers with very good circuit analysis background, Austin,
TX
To discover the many benefits of working for our client company,
fill out the form below or call Mike Buckley at 603-893-9486. All inquiries
will be held in the strictest confidence. Full relocation (domestic or
international, including VISA assistance) is available.
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Last updated on November 20, 2003
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