+ new - deleted ! changed Newsgroups: comp.lang.verilog,comp.answers,news.answers
Subject: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)
Followup-To: comp.lang.verilog
Reply-To: sjp@siliconlogic.com
Distribution: world
Summary: This posting contains a list of Frequently Asked Questions (and
their answers) about Verilog HDL.
Approved: news-answers-request@MIT.EDU
Archive-name: verilog-faq
Version $Id: verilog-faq.html,v 2.15 1995/06/20 16:48:25 sjp Exp sjp $
This is the FAQ (Frequently Asked Questions) list for the newsgroup comp.lang.verilog. It is an attempt to gather in one place the answers to common questions and to maintain an updated list of publications, services, and products. Please read this document before posting.
This article is posted bi-weekly. It is also available from the archive for this group.
If you haven't already done so, reading the posts on news.announce.newusers titled "A Primer on How Work With the Usenet Community", "Answers to Frequently Asked Questions about Usenet" and "Hints on writing style for Usenet" would be a good idea. They are "a guide to using it [Usenet] politely, effectively and efficiently."
Your comments, additions, and corrections to this list are welcome: Please send them to Steve Phillips <sjp@siliconlogic.com>.
+ new - deleted ! changed 
Table
of Contents Viewing
this article !
Where to get the most recent version of this FAQ How
does FTP work? 
What
is Verilog? Who's
bright idea was this? (A short history) What
is comp.lang.verilog? Is
there an archive for this group? Is
the archive available on the Web, through clients like Mosaic and Lynx?
Is
there a verilog.el for GNU emacs? What
is PLI? Is
there a version that runs on a IBM PC clone? What
is the best PC clone simulator? What
is the best workstation simulator? Is
there a vgrind def file? Is
there a free verilog parser available? Is
there a free Verilog simulator? Is
there a Verilog test suite? Where
can I find a free Verilog quick reference card? Are
there related Web sites?
Verilog
vendors and products Books
and Reference material on Verilog This article is now written as an HTML document. The plain text version is generated by dump the HTML with lynx. This means that it is no longer in digest format. This makes it a little less useable as a plain text document, but a lot nicer as a web ducument.
To skip to a particular question numbered xxx, use "/xxx" with most pagers. In GNU Emacs type "M-C-s xxx", (or C-r to search backwards), followed by ESC to end the search.
This FAQ is now available from the usual places:
RTFM FAQ archives
Ohio State Usenet
FAQ archives It is also posted frequently to comp.lang.verilog, and is available
from the archive site (see
Is
there an archive for this group? ).
FTP is a way of copying files between networked computers. If you need help in using or getting started with FTP, send e-mail to
mail-server@rtfm.mit.edu
with
send /pub/usenet-by-group/news.answers/ftp-list/faq
in the body.
Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 15000 active designers.
[contributed by Asad Khan <asad@Cadence.COM> ]
Verilog HDL originated circa 1983 at Gateway Design Automation, which was then located in Acton, MA. The company was privately held at that time by Dr. Prabhakar Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems.
Moorby built a simulator around Verilog-XL in 1984-85, and then went on to make his second major contribution at GDA, viz. the XL algorithm for every fast gate-level simulation, which was first productized in 1986.
Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989. Up till this time, Verilog HDL was still a proprietary language, being the property of Cadence Design Systems.
Cadence Design Systems decided to open the language to the public in 1990, and thus OVI was born.
[contributed by John Sanguinetti <jws@chronologic.com> ]
When OVI was formed in 1991, a number of small companies began working on Verilog simulators. The first of these came to market in 1992, and now there are mature Verilog simulators available from several souces.
As a result, the Verilog market has grown substantially. The market for Verilog-related tools in 1994 was well over $75m, making it the most commercially significant hardware description language on the market.
Verilog is now in the process of being standardized by the IEEE. There is an IEEE working group established under the Design Automation Sub-Committee which was established in 1993 to produce the IEEE Verilog standard 1364. This working group is currently active and expects to produce a draft standard for balloting sometime in 1995.
[extracted from ftp.uu.net:/usenet/control/comp/comp.lang.verilog.Z]
comp.lang.verilog is an unmoderated newsgroup which passed its vote for creation by 332:9 as reported in news.announce.newgroups on 12 Dec 1991.
For your newsgroups file:
comp.lang.verilog Discussing Verilog and PLI.
The charter, culled from the call for votes:
The USENET group is intended at providing a forum for the discussion of topics specific to Verilog, PLI (programming language interface), SDF (Standard delay file format), Synthesis guidelines, compliance and Verilog modeling. It will also provide users with an ability to share Verilog/PLI utilities. Users can also use the forum to discuss any Verilog related issues proposed by Open Verilog International and its organizational and technical committees.
Yes. Out of the goodness of our hearts, we here at Silicon Logic Engineering (SLE) provide an anonymous ftp archive for the postings to comp.lang.verilog and related files and information. This archive is read only; SLE does not allow non-employees to write into its file systems. If you have something to contribute, send it to me (sjp@cray.com) and I will upload it.
ftp.siliconlogic.com:/pub/comp.lang.verilog/
In addition, the University of Windsor maintains an archive of postings to several of the CAD related newsgroups. One of these is comp.lang.verilog:
ftp.cs.uwindsor.ca:/pub/local/vlsi/comp.lang.verilog/
SLE also provides space on the Silicon Logic Engineering Web Server for the Comp.lang.verilog home page:
http://www.siliconlogic.com/Verilog
In fact, this FAQ is actually a html document. The text version is created by dumping the html version with lynx. The html version can be accessed from the archive home page, or directly at:
http://www.siliconlogic.com/Verilog/verilog-faq.html
The archives contain no less than three verilog modes for emacs:
In addition, Cadence is now shipping an LSE (Language Sensitive Editor) that appears to consist of Lucid Emacs with a set of elisp files to implement the verilog mode.
PLI stands for Programming Language Interface. The PLI consists of an interface mechanism, a set of routines to interact with the simulation environment, and a set of routines to access the Verilog internal data structures. These allow user supplied C code to interact dynamically with the simulation and data structures.
See section
Verilog
vendors and products
The answer, of coarse, depends on what you are looking for. However, Yatin Trivedi has made available a summary of an evaluation of the PC clone verilog simulators currently available:
Here is the summary of the PC_based Verilog simulator
Product Evaluation results. These results and a discussion
of the evaluation appeared in ASIC & EDA Magazine, (Product
Evaluation, PC based Verilog Simulators, April 1994,
pages 12-36), and Electronic Engineering Times (Verilog
Simulators get benchmark grilling, April 25, Page 114).
A detailed report of raw performance numbers and the
scoring schemes are available in a report from Seva
Technologies (510-249-9085 or 408-223-1231).
The evaluation was ranked using SEVA Evaluation Index (SEI)
derived by talking with more than 50 different users.
SEI Criteria Weight
============ ======
Performance 40%
Debugging 20%
Environment
Language 15%
Compliance
Design Envr 10%
Integration
Tech Doc & 5%
Support
PLI Implem 4%
Specify Block 4%
Installation 2%
& Licensing
Performance was measured in terms of compile time, run time,
and memory used.
There were 9 different models run with small, medium, and
large number of vectors.
The 9 models were divided in small, medium, and large models
at gate level, RTL, and mixed.
More than 125 compliance test cases were run.
Run time was at least 3 minutes for the fastest simulator
to avoid any measurement inaccuracies.
Simulator/Vendor SEI Score SEI/$1,000
================ ========= ==========
VeriBest/Intergraph 73.9 4.93
FinSim/Fintronic 63.7 9.10
SILOS III/Simucad 62.3 20.77
Baseline/Frontline 61.9 10.32
Veriwell/Wellspring 29.7 29.85
Viper/InterHDL 25.9 26.03
Seva EValuation Academy Awards 1994 (SEVA Awards) goes to
(drum rolls, please...)
Serious User's Simulators ==> VeriBest, Silos III, Baseline
Best Price/Performance ==> Silos III, Baseline
Cost-conscious User's choice ==> Veriwell, Viper
Best Performance ==> VeriBest, Silos III
Most Compliant ==> Baseline, VeriBest
Best Documentation ==> Baseline, Silos III
Macintosh Compatibility ==> Veriwell
Note: VeriBest uses Finsim as its core simulator.
We hope this was a useful evaluation. The detailed report
is published for EDA managers who wish to make an informed
decision of purchasing large quantity of simulators for
their companies. Most individual users are better off just
buying the simulator from the above information rather
than spending $3,000 for the report.
If you happen to quote the information from this posting,
we request you to maintain the integrity of the information
in tact, and credit Seva Technologies as the source.
A VHDL simulator evaluation is near completion, and FPGA based
synthesis tools evaluation is planned for.
If you care to voice your opinion, we would like to know what
you thought of SEI criteria and weights for Verilog simulators
(VHDL are similar, and will be published in July issue of
ASIC & EDA magazine).
The designs we used for performance measurements were received
from REAL users under NDA, and most are in production. If you
would like your design to be part of a comprehensive evaluation
process, we would certainly welcome your participation.
Please read the articles in ASIC & EDA and EETimes.
Thank you for your interest. We look forward to your comments
directly by email to trivedi@netcom.com, lfs@mcimail.com, and
skk@netcom.com.
If you are in Europe, you may contact Mr. Jon Howes, NEuW, for
the availability of the report. His coordinates are:
Jon C Howes jchowes@neuw.demon.co.uk CIS: 100120,2101 Japan:SGS02201
NEuW Limited, PO Box 8, Greenfield Innovation Centre,Greenfield,Oldham,
OL3 7LZ, UK Tel:+44 (0) 457 820 326 Fax:+44 (0) 457 820 304
The answer, of coarse, depends on what you are looking for. However, Yatin Trivedi has made available a summary of an evaluation of the workstation based verilog simulators currently available:
SEVA Technologies, Inc. co-founders Yatin Trivedi and Larry Saunders, well-known industry consultants, organized and conducted these evaluations, third in an ongoing series. The evaluations are based on the SEVA Evaluation Index (SEI), which is a comprehensive set of evaluation criteria developed by SEVA. The relative importance of the criteria is derived from inputs of end users/designers, project managers at system houses, and EDA tool developers. The SEI is continually refined with inputs received from previous Verilog and VHDL evaluations. Besides raw performance, the index is weighted by measures such as language compliance, debugging capability, integration with the design environment, programming language interface (PLI), ability to handle a design's timing data (SDF), product documentation, installation and licensing, and technical support. SEVAFs evaluation criteria and results, including the SEI distribution and ranking based on the SEI, are summarized below. SEI Criteria Weight Vendor SEI Score Performance 50 Chronologic 82.14 (Compile+Run+Memory) Cadence 69.31 Language Compliance 20 Intergraph 47.24 Debug Commands 10 Simucad 36.86 Design Env Integration 6 CAD Artisans 23.49 PLI Support 6 Wellspring 23.15 SDF and Timing 6 interHDL 22.96 Documentation & 2 Technical Support An article outlining the evaluation results are published in the March, 1995 issue of "Integrated System Design" magazine. Complete results and the details of the evaluation methodology can be obtained by subscribing to SEVA's Newsletter The Ultimate EDA Tool.
Yes. Available in the archives as:
ftp.siliconlogic.com:/pub/comp.lang.verilog/verilog-vgrind-def.Z
Yes. There are two known public domain parsers.
hdl.y below is a verilog parser written using the Unix utility - yacc. It by no means is a complete verilog parser. This only represents a few nights of effort in front of the ole PC. This is donated in the hope that this will enable additional work by individuals interested in learning verilog & yacc.
I ran across a verilog-HDL parser authored by stcheng@ic.berkeley.edu. It is available by anonymous FTP from ic.berkeley.edu in directory /pub/stcheng/vl2mv.tar.Z. It is part of a verilog->bliff translator. It comes complete with a wrapper for the translator, and contains the parser and code to build the parse tree. One of the handiest things is a traverse routine which echoes the input file back to the output by traversing the data structures, thus giving you a template to base your own application on.
The parser itself seems to contain most of the verilog-HDL grammar, though many behavioral constructs are unimplemented in the data structure routines. It is still under development, so there are bugs. I spent a few days hacking the code and removed a lot of hooks to berkeley OCTTOOLS code that wasn't included with the distribution. The code as I downloaded it didn't compile. I'll place this on the anonymous FTP site here (ftp.eecs.umich.edu in people/riepe) - you'll get a version that compiles (at least it does on my decstation) and a list of bug fixes that have been sent to me other people I've given it to.
Bug reprts/fixes should be sent both to riepe@eecs.umich.edu, and stcheng@ic.berkeley.edu (the author of the original version)
There is a free, copylefted Verilog simulator called "vbs", written by Jimen Ching and Lay Hoon Tho as a senior design project in the electrical engineering curriculum of the University of Hawaii, College of Engineering.
It is available from the archive at:
It appears that Veriwell/386 and Veriwell/Sparc are now shareware. Use is free for source files under 1000 lines. For larger files, a hardware dongle is required for the MS-DOS version, a license for the Sparc version. The simulator is available for downloading from the Wellspring Solutions BBS or via ftp:
InterHDL also has shareware version. Eli Sternheim says "This is a full Verilog simulator with the following exceptions: no PLI, specify blocks are ignored, no switch level constructs but gates and primitives are supported. Also there is a size limitation on the design."
InterHDL's simulator can also be had through their mailserver. send an e-mail to request@interhdl.com with the word "help" in the body of the message.
[contributed by Rich Kolb <rich@systems.com>]
The OVI Test and Compliance Committee has acquired Verilog HDL tests and organized them into a test suite. Most of the tests are very small "atomic" tests that test one particular portion of the language. Each test consists of the Verilog circuit file and the simulation output file produced by OVISIM. OVISIM is the Verilog clone produced by Cadence and contributed to OVI.
To induce organizations to contribute additional tests, the entire test suite is available to anyone who contributes 25 tests or tests with at least 1000 lines of Verilog code. Currently there are more than 400 tests in the test suite (9/12/84). Naturally, OVI would appreciate it if even more tests were submitted. OVI would like to see as many tests shared by the Verilog community as possible.
The test submission system is set up to automatically function by e-mail. Tests can be mailed to the test system and it will run the simulations and send back the results.
OVI welcomes all contributed tests. If a developer is only interested in the simulation results from a single circuit, that circuit can be sent to the test system and the simulation results will be returned.
For more information on the test submission format and procedure, send mail to rich@systems.com
In the archive, of coarse! A postscript quick reference card has been donated by Rajeev Madhavan. It is available in the archive:
ftp.siliconlogic.com:/pub/comp.lang.verilog/ref.tar.Z
Here are some links to Verilog related sites:
Caveat: Many of these product descriptions were written by the vendor. They may contain hype.
HDS includes a library-based HDL generator which generates optimized Verilog (VHDL) code, targetted for specific synthesis tools. In addition, HDS includes an HDL-Import capability, which allows designers to co-simulate system-level diagrams with Verilog (VHDL) code.
The product will be available in the first quarter of 1995.
The software is built around a high-performance concurrent fault simulator that supports all of the unidirectional primitives, wire types, and gate/net delays defined in the Verilog 2.0 LRM. UDPs are also supported, along with optimized built-in models for single and multi-port RAMs.
It is not necessary to sacrifice accuracy for fast fault simulation.
The software supports the detailed pin timing and strobing features found on "tester-per-pin" ATE.
TDX_FSIM - highly accurate, fast fault simulator with full timing and states/strengths.
TDX_IDDQ - flexible, programmable transistor-short fault simulation and vector selection for current measurement testing.
TDX_STEP (TM) - static and dynamic testability analysis, and test improvement program that supports both scan and non-scan designs.
TDX_ATG - sequential test generation for scan and non-scan designs. Tightly integrated with tdx_fsim, tdx_step, and tdx_iddq.
Free demo executables are available by anonymous ftp from ftp://ftp.netcom.com/pub/at/attest. The demo software runs on any small circuit, and also on an 8085 microprocessor clone model that is available at the ftp site.
Features Include:
ABT, ACT, ALS, AS, BCTTTL, HCT, F, S, LS Series Glue logic parts.
FIFOs, MEMORIES and PAL models are available for some families, others can readily be developed on needed basis.
Partial Function or Bus Function Models can be developed at a nominal cost.
Signalscan supports simultaneously viewing signals from mixed simulation environments, including Cadence's Verilog, Chronologic's VCS, Fintronic's FinSim, Frontline's BaseLine and SimLine, Ikos' Gemini, SIMUCAD's SILOS, EPIC's TimeMill and PowerMill and Meta Software's HSPICE.
FinSim 2.0 was rated the fastest PC-based Verilog simulator in the published benchmark comparison from Integrated Design System (formerly ASIC & EDA). With FinSim 4.0, simulator run up to 40x faster while utilizing less memory. PLI and SDF access is greatly optimized. In addition, FinSim 4.0 has several new features including incremental compilation and full support for source level debugger from Design Acceleration Signalscan and Veritools Undertow.
FinSim supports VCD waveform display tools from Design Acceleration, Veritools, and Systems Science. Schematic capture system is supported from Data I/O. FinSim is also the core simulation engine in the Intergraph Veribest Design System.
FinSim has a list price from $995 to $10,000 for all platforms. Prices reflect single license per machine. Multiple and educational discounts are available. Evaluation version of FinSim is available upon request.
Electronics Desktop Manager - Our electronics specific graphical desktop which organizes design data and launches applications. The Electronics Desktop manager includes the Design Methodology Manager, a tool that allows software products to be organized into an enforced process oriented flow (e.g., the steps required to build an ASIC or FPGA as specified by a silicon vendor).
ACEPlus Design Entry System - Our front-end design entry editor that utilizes hierarchical design to organize the use of primitive symbols and representative blocks for Verilog source files or State diagrams.
ACEPlus Designer - Our automatic HDL generator that takes schematics and state diagrams created with ACEPlus Design Entry System and automatically generates simulatable VHDL, Verilog HDL, or ABEL HDL.
VeriBest Simulator - Our high performance, high capacity Verilog-XL compatible simulator which includes VeriScope, our graphical waveform viewer and simulation controller.
Both Veribase and Verinet are toolkits which have a library of API/PLI functions for accessing the design database.
Stimgen automatically synthesizes the timing behavior of the ASIC cell and generates stimuli for characterizing each of the timing and electrical parameters of the cell.
Libchar is the automatic characterizer, which measures each of the electrical parameters and fits them into one of several delay models. Verigen converts ACDL descriptions into structural verilog complete with specparams and pin-to-pin paths using the parameters calculated by libchar.
Syntest converts ACDL descriptions into RTL verilog, to be used for verifying synthesis libraries and technology mapping.
Veritest generates a testbench to verify the functionality of the verilog representations of the cell.
Thirty day free trial. Detailed release notes emailed upon request.
Simultaneous Test (TM) Option, a unique SpeedSim/3 option, allows up to 32 different tests, such as diagnostics or application program streams, to run simultaneously on the same image of a design model. Simultaneous Test boosts performance 5 to 32 times over the base SpeedSim/3 product.
Symmetric Multi-Processing (SMP) option was built from the start to get the most out of SMP technology. It's unique Multithread management techniques can deliver near linear performance gains on up to eight processors implemented in a single system. These processors work in tandem simulating a single model that yields great efficiency on a shared memory system. Users can economically increase performance simply by plugging in additional processors. This is particularly attractive for designs over 500,000 logic gates where engineers can get much faster turnaround on a long test using the SpeedSim/3 SMP option. With large designs, SpeedSim/3 users will realize near linear performance increases with minimal memory impact when they add additional processors.
POWERFAULT - A push-button IDDQ solution for Verilog designs. It finds near-optimal IDDQ vectors, and generates detailed fault coverage reports. It can be used in conjunction with conventional fault simulators to increase the coverage, or independently, by itself. Handles both "stuck-at" and "short" faults.
POWERSIM - Get accurate power information, at an early stage in the design. Use your unmodified Verilog-HDL sources, plus backannotated capacitance and voltage information. Compute the dynamic power usage for the whole circuit, or for portions of the hierarchy. Avoid heat, power, and metal migration problems.
VERA - A design verification system, which allows design and verification engineers to thoroughly exercise complex Verilog circuits. Users create compact and powerful test benches in the high level Vera language. Vera verifies the design by simulating the test bench, while it talks via PLI with a Verilog simulator that simulates the design.
VERITY - A kit for tool developers that handles the full Verilog-HDL language, and provides the following self-contained modules with their corresponding APIs: (a) parser, (b) hierarchical database builder and navigator, (c) elaborator and flattener, (d) behavioral to compiled code (machine code for SPARC, C for other architectures), and (e) fault divergence and convergence.
First and foremost, V.C.S. apologizes deeply for the inconvenience and concern that this action may have caused you, the VCS user community. We feel a strong loyalty to you and know that our leaving does not make your job easier.
We are available to help you with any questions you may have about VCS. We cannot make enhancements or changes to the product -- we don't have the source code. However, we are available to answer questions on general usage, ways to use VCS more efficiently or suggestions on how to work around the occasional bug. We don't want you to be dead in the water.
We are also available for general Verilog HDL consulting and training. We represent experts in Verilog HDL, auxiliary programs using PLI and of course, a lot of knowledge about how to best use VCS. While we are working on an agreement with Viewlogic, we are available to help on your projects. We have a lot of energy and want to devote it to solving problems important to our customers. We look forward to hearing from you.
This offer of help should in no way be construed as competitive to VCS or Viewlogic. We are not currently available to write a new simulator or consult on how to make a competing simulator faster. We hope to apply that knowledge to VCS again one day soon.
Please feel free to contact any of us with questions.
Veritools software is available via anonymous ftp at netcom.netcom.com (192.100.81.100) in the directory pub/veritools.
VeriWell/Free for MS-DOS, Windows, Macintosh, Sparc, and Linux is a full-featured free version of the VeriWell simulator available via BBS at 1-508-865-1113 and via anonymous ftp at ftp://iii.net/pub/pub-site/wellspring/...
[provided by Cliff Cummings - cliffc@qualis.com]
Alphabetical listing of materials by category:
* New or revised since REF_FAQ v1b0
(acknowledgement to Fjthomas@aol.com for corrections)
VERILOG REFERENCE MATERIALS
===========================
*(R3) "DIGITAL DESIGN AND SYNTHESIS WITH VERILOG HDL", by
E. Sternheim, R. Singh, Y. Trivedi, R. Madhavan and
W. Stapleton
*(R2) "DIGITAL DESIGN WITH VERILOG HDL", by
E. Sternheim, R. Singh and Y. Trivedi
*(R7) Feature Columns by L. Saunders and Y. Trivedi, regular
columns in Integrated System Design Magazine
(formerly ASIC & EDA Magazine)
(R4) "QUICK REFERENCE FOR VERILOG HDL", by
R. Madhavan
*(R6) "SUCCESSFUL ASIC DESIGN THE FIRST TIME THROUGH", by
J. Huber and M. Rosneck
(R1) "THE VERILOG HARDWARE DESCRIPTION LANGUAGE", by
D. Thomas and P. Moorby
NEW*(R8) "THE VERILOG HARDWARE DESCRIPTION LANGUAGE, Second
Edition", by D. Thomas and P. Moorby
*(R5) "VERILOG HDL 2.0 LANGUAGE REFERENCE GUIDE", by
Sutherland HDL Consulting
OPEN VERILOG INTERNATIONAL (OVI) REFERENCE MATERIALS
====================================================
(O6) "1993 OVI DIRECTORY OF SUPPORT FOR VERILOG HDL"
*(O1) "LANGUAGE REFERENCE MANUAL" (LRM), Version 2.0
(O7) "OPENEXCHANGE"
(O8) "OPENEXCHANGE" (Back Issues)
*(O4) "PROCEEDINGS FROM '92 OVI USER GROUP MEETING"
*(O5) "PROCEEDINGS FROM '93 INT'L VERILOG HDL CONF."
NEW*(O9) "PROCEEDINGS FROM '94 INT'L VERILOG HDL CONF."
*(O2) "PROGRAMMING LANGUAGE INTERFACE" (PLI), Version 2.0
*(O3) "STANDARD DELAY FILE FORMAT MANUAL" (SDF), Version 2.0
VENDOR REFERENCE MATERIALS
==========================
(V4) "CADENCE VERILOG TRAINING COURSE LABS & SOLUTIONS"
(V3) "CADENCE VERILOG-XL TRAINING COURSE"
(V2) "GRAPHICAL OUTPUT FOR THE VERILOG PRODUCT FAMILY REFERENCE"
(V5) "VERILOG HDL TRAINING COURSE", by Sutherland HDL Consulting
(V1) "VERILOG-XL REFERENCE MANUAL"
REF_FAQ REFERENCE-INCLUSION POLICY
==================================
VERILOG REFERENCE MATERIALS
===========================
(R1) "THE VERILOG HARDWARE DESCRIPTION LANGUAGE", by D. Thomas
and P. Moorby.
ISBN 0-7923-9126-8
: | :
Kluwer Academic Publishing Co. | Kluwer Academic Publishers Group
Order Department | Order Department
P.O. Box 358 | P.O. Box 322
Hingham, MA 02018 | 3300 AH Dordrecht
| The Netherlands
Phone: 617-871-6600 | Phone: +31 78 524400
FAX: 617-871-6528 | FAX: +31 78 524474
e-mail: kluwer@world.std.com | e-mail: services@wkap.nl
- Text examples are available upon e-mail request to
thomasmoorbybook@cadence.com
- A personal favorite. Good insights into the Verilog
language by P. Moorby, one of the original authors of
Verilog. (Submitted by Cliff Cummings)
(R2) "DIGITAL DESIGN WITH VERILOG HDL", by E. Sternheim, R. Singh
and Y. Trivedi.
ISBN 0-9627488-0-3
Automata Publishing Company,
1072 S. Saratoga-Sunnyvale Rd., Bldg. A107, San Jose, CA 95129
Phone: 408-255-0705
FAX: 408-253-7916
E-mail: << unknown >>
Or Contact Raj Singh, Phone: 415-428-4200
E-mail: rajvir@interhdl.com
- Comes with a DOS-format floppy disk which includes all text
examples.
- Only complaint is that the book has no index.
- Y. Trivedi has a regular column in Integrated System Design
magazine.
(Submitted by Cliff Cummings)
(R3) "DIGITAL DESIGN AND SYNTHESIS WITH VERILOG HDL", by E. Sternheim,
R. Singh, Y. Trivedi, R. Madhavan and W. Stapleton.
ISBN 0-9627488-2-X
Automata Publishing Company,
1072 S. Saratoga-Sunnyvale Rd., San Jose, CA 95129
Phone: 408-255-0705
FAX: 408-253-7916
E-mail: << unknown >>
Or Contact Raj Singh, Phone: 415-428-4200
E-mail: rajvir@interhdl.com
- Revised edition of (R2) with added 75 page Synthesis
chapter, 60-page Verilog HDL semantics chapter, and can
be purchased with a PC Verilog Simulator.
- This book DOES have an index.
- PC Simulator: "This is a full Verilog simulator with the
following exceptions: no PLI, specify blocks are ignored,
no switch level constructs but gates and primitives are
supported. Also there is a size limitation on the design."
(from Eli Sternheim).
(R4) "QUICK REFERENCE FOR VERILOG HDL", by R. Madhavan
ISBN 0-9627488-4-6 - 1993
Automata Publishing Company,
1072 S. Saratoga-Sunnyvale Rd., #A107, San Jose, CA 95129
Phone: 408-255-0705
FAX: 408-253-7916
E-mail: help@apc.com
Or Contact Raj Singh, Phone: 408-749-8775, FAX: 408-749-8823
E-mail: rajvir@interhdl.com
Automata Verilog Quick Reference
================================
Advantages: - 24 pages - Spiral Bound.
- Intended to provide a quick reference for
semantics and examples.
- 3-page section on Synthesis supported/unsupported
constructs.
Disadvantages: - 24 Table of Content entries. No index.
- Synthesis section reportedly differs from the OVI
synthesis guidelines.
- Lists Net data types but not all of the Reg data
types, pp 2-3.
- Missing keywords: casex, casez, edge, endspecify,
macromodule, strength, xnor, xor, pg 4.
- Only lists 4 compiler directives, omits `timescale
(among others), pp 3-4
- Lists only three $system tasks ($time, $finish,
$setuphold scattered throughout examples).
- Typo: Combinational 3:1 MUX UDP example mis-labeled
as "inverted out", pg 7.
- Other minor omissions.
Recommendation: The Quick Reference would be enhanced by a
fine-print keyword and key-topic index inside the back cover.
(Note from Rajeev Madhavan: many of the above issues will be
addressed in the pending next revision)
(Submitted by Cliff Cummings)
(R5) "VERILOG HDL 2.0 LANGUAGE REFERENCE GUIDE", by Sutherland HDL
Consulting - Nov 1994
Sutherland HDL Consulting, 2417 Redwood Ct.
Longmont, CO 80503
Phone: 303-682-8864
FAX: 303-682-8864 (same number)
E-mail: stuart@sutherland.com (Stuart Sutherland)
Sutherland Verilog Quick Reference
==================================
Advantages: - 24 pages.
- Intended to be a quick reference language
syntax guide.
- Lists 16 compiler directives including `timescale.
- Lists ~25 $system tasks, including 7
specify-block timing checks, $monitor,
$display, $stop, file-I/O tasks.
- Based on March 1993 - OVI 2.0 Spec (includes
some newer Verilog constructs)
Disadvantages: - 44 Table of Content entries. No index.
- No Synthesis section (but not necessarily
useful to, or needed by all Verilog users).
Recommendation: The Quick Reference would be enhanced by a
fine-print keyword and key-topic index inside the back cover.
(Submitted by Cliff Cummings)
(R6) "SUCCESSFUL ASIC DESIGN THE FIRST TIME THROUGH", by
J. Huber and M. Rosneck.
ISBN 0-442-00312-9
Mark Rosneck's e-mail address: mark_rosneck@mentorg.com
Van Nostrand Reinhold
Mail Order Department
P.O. Box 668
Florence, KY 41022-0668
1-800-354-9706
(The material in this book is) not limited to Verilog, but
it does give a good, practical introduction to the processes
and tradeoffs involved in designing an ASIC. (Submitted by
Daniel Sears)
(R7) Feature Columns by L. Saunders and Y. Trivedi, regular columns
in Integrated System Design Magazine (formerly ASIC & EDA Magazine)
Integrated System Design
5150 El Camino Real Ste D31,
Los Altos, CA 94022-9873
Free subscription for qualified readers:
To qualify by phone: (800) 643-READ (7323)
Subscribe onlnie to http://www.netline.com/isd
Interactive online subscription number: telnet asic.com 2110
Monthly (occasionally missed) column covering Verilog and
VHDL modeling topics. Well worth reading. (Submitted by Cliff
Cummings)
(R8) "THE VERILOG HARDWARE DESCRIPTION LANGUAGE, Second Edition",
by D. Thomas and P. Moorby.
ISBN 0-7923-9523-9
: | :
Kluwer Academic Publishing Co. | Kluwer Academic Publishers Group
Order Department | Order Department
P.O. Box 358 | P.O. Box 322
Hingham, MA 02018 | 3300 AH Dordrecht
| The Netherlands
Phone: 617-871-6600 | Phone: +31 78 524400
FAX: 617-871-6528 | FAX: +31 78 524474
e-mail: kluwer@world.std.com | e-mail: services@wkap.nl
This fully revised Second Edition features:
-- new and more detailed examples
-- a more formal presentation of the language
-- comprehensive cross-references for each section
-- a disk containing a DOS version of the VeriWell(tm)
Verilog simulator as well as examples from the book.
The simulator can be used to solve the examples.
(Submitted by Eric Maki of Kluwer Academic Publishers)
OPEN VERILOG INTERNATIONAL (OVI) REFERENCE MATERIALS
====================================================
OVI is the organization charged with Verilog standardization
and language enhancements. OVI is currently pursuing Verilog
IEEE and ISO standardization.
For the following publications contact Lynn Horobin at the
OVI office.
Open Verilog International
Lynn Horobin
15466 Los Gatos Blvd., Suite 109-071
Los Gatos, CA 95032
Phone: (408) 353-8899 -- FAX: (408) 353-8869
e-mail: ovi@netcom.com
(O1) "LANGUAGE REFERENCE MANUAL" (LRM), Version 2.0*
- $100 per copy, plus local sales tax
(O2) "PROGRAMMING LANGUAGE INTERFACE" (PLI), Version 2.0*
- $150 per copy, plus local sales tax
(O3) "STANDARD DELAY FILE FORMAT MANUAL" (SDF), Version 2.0*
- $100 per copy, plus local sales tax
(O4) "PROCEEDINGS FROM '92 OVI USER GROUP MEETING",
< sold out >
(O5) "PROCEEDINGS FROM '93 INT'L VERILOG HDL CONF.",
< sold out >
(O6) "1994 OVI DIRECTORY OF SUPPORT FOR VERILOG HDL",
- No charge
(O7) "OPENEXCHANGE", monthly OVI publication,
- No charge
(O8) "OPENEXCHANGE" (Back Issues), monthly OVI publication,
- $5 per copy
(O9) "PROCEEDINGS FROM '94 INT'L VERILOG HDL CONF.",
- $50 per copy, plus local sales tax
* Versions 1.0 of the LRM, PLI and SDF are still available.
VENDOR REFERENCE MATERIALS (Have requested an update from Cadence)
==========================
(V1) "VERILOG-XL REFERENCE MANUAL", 3 Volumes, Version 1.6c June
1993 (Contact your local Cadence sales office)
- A good set of reference manuals with examples, after you
have learned Verilog, or if you have a specific question.
(Submitted by Cliff Cummings)
(V2) "GRAPHICAL OUTPUT FOR THE VERILOG PRODUCT FAMILY REFERENCE
MANUAL", Version 1.1f September 1989, Version 1.1f September
1989 Release notes, Version 1.2b November 1990 Release notes.
(Contact your local Cadence sales office)
- Explains the commands that are used with the GR_WAVES graphics
package. (Submitted by Cliff Cummings)
(V3) "CADENCE VERILOG-XL TRAINING COURSE", Version 3.3, August 1991.
(Contact your local Cadence sales office)
- Reasonable training materials.
- A number of the training slides contain examples with minor
syntax errors and other examples that must be corrected before
they will run (it is obvious that not all of the training
examples were tested).
- The training course notebook does not have an index and really
needs one. (Submitted by Cliff Cummings)
(V4) "CADENCE VERILOG TRAINING COURSE LABS & SOLUTIONS", Release 3.3.a
April 14, 1992. (Contact your local Cadence sales office)
- No index, but a good set of labs to accompany the training
course. (Submitted by Cliff Cummings)
(V5) "VERILOG HDL TRAINING COURSE", by Sutherland HDL Consulting
Sutherland HDL Consulting, 2417 Redwood Ct.
Longmont, CO 80503
Phone: 303-682-8864
FAX: 303-682-8864 (same number)
E-mail: stuart@sutherland.com (Stuart Sutherland)
REF_FAQ REFERENCE-INCLUSION POLICY
==================================
If anyone is aware of other Verilog reference materials, please
forward the information to Cliff Cummings -
cliffc@qualis.com
REF_FAQ Reference-Inclusion Policy:
(1) Materials should be released and publicly available
(pre-release announcements will no longer be included in
REF_FAQ).
(2) Publisher/Vendor pricing information will be added only upon
Publisher/Vendor request (exception: OVI published prices
have been noted).
(3) Reviews, if added, will be credited to the reviewer.
(4) Magazines will only be listed if they carry a regular
Verilog-related column (such as Integrated System
Design(R7)).
(5) These policies are subject to suggestions and change!